National Institute of Technology, Agartala
Special Manpower Development Program for Chip to System Design.


Seeing the impact of SMDP-I and SMDP-ll Ministry of Electronics & Information Technology (MeitY), Govt. of India is promoting Electronics System Design. Thus, there is a need to initiate an integrated program entitled "Special Manpower Development for Chips to System", which not only aims at developing specialized manpower in VLSI but also emphasises on development of working prototypes of System on Chip / System using mostly ASICs / ICs designed in the program. This will, therefore, be a step towards bringing a "SoC /System" development culture in academic institutions across the country through collaborative efforts of Resource Centres (RC) and Participating Institutions (PI).

National Institute of Technology, Agartala is a participating institute associated with IIT Guwahati (Resource Centre) and others participating institutions are NIT Arunachal Pradesh, NIT Manipur, NIT Meghalaya, NIT Mizoram, NIT Nagaland. VLSI design laboratories with advanced EDA tools have been set up to be used by the Participating Institutions. It provides several resources for the use of students, staffs and faculties. The EDA tools and information are being used in the various courses taught during the course of Post-Graduate and Research Programs.

The main objectives of the SMDP-C2SD Project!

i. Bring in a culture of System on Chip / System designing by developing working prototypes with societal applications
ii. Capacity building in the area of VLSI/ Microelectronics and Chip to System development.
iii. Broaden the base of ASIC / IC designing in the country
iv. Broaden the R&D base of Microelectronics / Chip to System through networked PhD program
v. Promote "Knowledge Exchange Program"
vi. Protection of Intellectual Property generated

The main Project objectives of NIT Agartala!

i. To build an air quality monitoring system based on FPGA/ASIC platform which will detect the presence of CO, CO2, NO2 gases along with temperature and humidity of the ambience around it covering an area. It is intended to be deployed in various parts of the north-eastern region of the country.
ii. Efficient hardware (FPGA/ASIC) realization of Emperial Mode Decomposition Algorithm for filtering and trending application.
iii. Generating Manpower in the field of VLSI Design and ESDM.

Chief Investigator

Dr. Sambhu Nath Pradhan
Associate Professor
ECE,Nit Agartala

Design and developed by Vivek Kumar Singh
National Institute of Technology, Agartala